1. Field of the Invention
This invention relates to the fabrication of microstructures, and in particular to the fabrication of microstructures with a vacuum-sealed cavity, for example containing a moving component, and further to the manufacture of Micro-Electro-Mechanical-Systems (MEMS), such as micro-gyroscopes, micro-accelerometers, resonant accelerometers, micro-mirrors, micro-motors, micro-actuators and other such micro-devices.
2. Description of Related Art
The integration of micro-devices with a moving component creates a very serious packaging challenge for several reasons. Some MEMS-based devices require the encapsulation to be done before dicing so that they are protected against micro-contamination from particles and dicing slurry while being processed like a standard semiconductor chip, without the need for dedicated equipment or processes for dicing, mounting and molding procedures inside the cleanrooms. Changes in atmospheric conditions can change the capacitance readout of micro-gyroscopes and micro-accelerometers without any changes in acceleration and because an increased relative humidity can increase friction of their moving parts, it is necessary to encapsulate their moving and/or particular components in vacuum or in a controlled atmosphere. Most MEMS-based resonant accelerometers, MEMS-based RF switching devices and other such MEMS devices have very serious Q-factor degradation when exposed to an ambient pressure exceeding 1 Pa. Their moving MEMS components require a vacuum packaging to a residual pressure of less than 1 Pa to ensure a reliable service during its complete projected life.
U.S. Pat. No. 5,589,082, entitled, “Microelectromechanical signal processor fabrication”, the contents of which are incorporate by reference herein, discloses a first example of such protective packaging. The micro-cavity described in this patent is used to protect a micro-mechanical resonator and is formed using a vacuum sealed silicon nitride micro-shell fabricated by properly micromachining the micro-mechanical resonator in a certain fabrication step; depositing a 7.0 μm thick phosphosilicate (PSG) layer over the micromachined micro-mechanical resonator; patterning the 7.0 μm thick PSG layer into an isolated island covering the moving and/or particular component of the micromachined micro-mechanical resonator and defining the shape of the micro-shell; depositing an extra 1.0 μm thick PSG layer; patterning the lateral etch-channels at the periphery of the isolated island; depositing an extra 1.0 μm thick LPCVD low-stress silicon nitride; patterning the lateral etch holes in the silicon nitride located at the periphery of the isolated island; releasing the micro-mechanical resonator using concentrated HF penetration through the lateral etch holes formed at the periphery of the isolated island of all sacrificial material located under and over (7.0 μm thick PSG layer) the moving and/or particular component of the micromachined micro-mechanical resonator, leaving the formed 1.0 μm thick LPCVD low-stress silicon nitride micro-shell intact; and sealing of the lateral etch holes formed at the periphery of the formed micro-shell using a 2.0 μm thick layer of silicon nitride deposited over the suspended 1.0 μm thick LPCVD low-stress silicon nitride micro-shell, as to form a 3.0 μm thick LPCVD low-stress silicon nitride micro-shell.
As indicated in this patent at column 11, lines 7-12, the release of the micro-mechanical resonator using concentrated HF through the lateral etch holes formed at the periphery of the silicon micro-shell limits the size of the micro-device to about 500 μm×500 μm due to incomplete sacrificial material removal away from the periphery of the micro-shell; and collapse of the 3.0 μm thick LPCVD low-stress silicon nitride micro-shell upon exposure to atmospheric pressure.
A second example of protective packaging is given in U.S. Pat. No. 5,668,033 entitled ‘Method for manufacturing a semiconductor acceleration sensor device’. The packaging technique described this patent and used to fabricate the packaging structure covering the acceleration sensor uses a gold-silicon (case where a silicon-on-insulator substrate is used) or a gold-polysilicon eutectic bonding technique. This technique requires the bonding of two substrates.
A third example of protective packaging is disclosed in U.S. Pat. No. 5,783,749 entitled ‘Vibrating disk type micro-gyroscope’ (Electronics and telecommunications research Institute). The vacuum sealed packaging structure covering the gyroscope to maintain a 1 mTorr pressure to enhance its sensitivity and to minimise air damping uses an unknown bonding technique. This technique also requires the bonding of two elements, i.e. of a sealed structure and of a substrate, as indicated in column 3, lines 25-31.
A fourth example of protective packaging is disclosed in U.S. Pat. No. 5,952,572 entitled ‘Angular rate sensor and acceleration sensor’ (Matsushita Electric Industrial Co., Ltd.). Three substrates composing the angular rate sensor are bonded together as a sandwich structure using anodic bonding, as mentioned in column 7, lines 36-41. This anodic bonding requires the silicon and glass substrates to be heated at 300-400° C. in a vacuum while a negative voltage of about 1000V in terms of reference potential of the silicon substrate is applied to the glass substrates. As mentioned at column 7, lines 55-58, a Zr—V—Fe/Ti non-volatile getter material is also integrated in the sealed cavity to maintain the vacuum quality. This technique also requires the bonding of two substrates.
A fifth example of such protective packaging is provided by U.S. Pat. No. 6,140,144 entitled ‘Method for packaging microsensors’ (Integrating Sensing Systems, Inc.). Two substrates composing the microsensors are bonded together by flip chip bonding using an underfill material as to maintain a controlled pressure/controlled environment around the sensing element, as mentioned in column 3, lines 48-50. This technique also requires the bonding of two substrates.
A sixth example of such protective packaging is given in U.S. Pat. No. 6,232,150 entitled ‘Process for making microstructures and microstructures made thereby’ (The Regents of the University of Michigan). The two substrates composing the microstructures described are bonded together with a localised micro-heater flip chip bonding technique using a bonding material and a metal-based localised resistive micro-heater capable of locally heating the bonding material as to provoke the bonding of the two substrates, as mentioned in column 4, lines 25-35. This technique also requires the bonding of two substrates.
A seventh example of such protective packaging is given in U.S. Pat. No. 6,265,246 entitled ‘Microcap wafer-level package’ (Agilent Technologies, Inc.). The base wafer integrating a micro-device is bonded to a matching cap wafer using cold welding of the bonding pad gaskets of the cap wafer to the periphery of the bonding pads of the base wafer integrating the micro-device. The arrangement assures a hermetic seal of the wafer-level package and electrical connections to the micro-device without passing through a seal. This technique also requires the bonding of two substrates.
An eighth example of such protective packaging is given in U.S. Pat. No. 6,297,072 entitled ‘Formation of a microstructure having an internal cavity’ (Interuniversitair Micro-Electronika Centrum, IMEC, VZW). A first chip located on first substrate covered with antimony-copper or antimony-nickel/gold metallization seed layer forming a stable intermetallic compound with a selected solder is bonded to a second chip located on a second substrate also covered with antimony-copper or antimony-nickel/gold metallization seed layer via an antimony-lead, an antimony-lead-silver, an indium, a gold-antimony, an antimony-silver, an antimony-silver-copper or an antimony-bismuth electroplated solder ring capable of being reflowed at 200-350° C. as to create an enclosed vacuum or controlled ambient cavity. This technique also requires the bonding of two substrates.
A ninth example of such protective packaging is given in U.S. Pat. No. 6,335,224 titled ‘Protection of microelectronic devices during packaging’ (Sandia Corporation). A released MEMS element is protected by a water-insoluble vacuum vapor deposited conformal and dry-etchable temporary protective coating, such as parylene, during dicing, allowing its protection against micro-contamination. This protective coating is later removed using an oxygen plasma when the diced MEMS or IMEMS device substrate is bonded to the package and when the bond pads of the MEMS device are electrically connected to the external electrical leads with bond wires. Following the removal of the protective coating, a cover lid including an optional optical window is bonded to the package protecting the released MEMS element. This technique requires a temporary protective coating to be removed using an oxygen plasma during die packaging, just prior to cover lid bonding.
A tenth example of the importance of such protective packaging is described by Samsung Corporation in a number of papers. As shown in FIG. 1, the paper by B. Lee, S. Seok, J. Kim, and K. Chun, ‘A mixed micromachined differential resonant accelerometer’, Work supported by ADD (Agency for Defense Development) through ACRC (Automatic Control Research Center) under Grant AC-041 and by the Brain Korea21 Project, discloses a vacuum packaging technique using anodic bonding of a handle glass wafer to a Chemical-Mechanical Polished (CMP) 6 μm thick polysilicon deposited on a previously deposited and patterned TEOS sacrificial layer, polysilicon electrodes and dielectric isolation layers on a silicon substrate which is flipped-over and CMPed again on its back side to a thickness of 40 μm, then micromachined using deep RIE (Reactive Ion Etching), released to produce the MEMS accelerometer and then anodically bonded to another glass substrate under vacuum to produce a vacuum sealed accelerometer.
As shown in FIG. 2, the paper by B. Lee, C. Oh, S. Lee, Y. Oh and K. Chun, ‘A vacuum packaged differential resonant accelerometer using gap sensitive electrostatic stiffness change effect’, Work supported by ADD (Agency for Defense Development) through ACRC (Automatic Control Research Center) under Grant AC-04, describes Samsung's use of anodic bonding of two substrates to produce the accelerometers, but here shows the effect of the vacuum level around the accelerometer on the Q-factor of its parallel plate resonators. The presence of residual gas (air) is the cause of the observed damping effect. This reference discusses the effect or residual gases on the performance of MEMS devices and explains the need for a vacuum sealed approach.
As shown in FIG. 3, the paper by Y. Gianchandani, H. Kim, M. Chinn, B. Ha, B. Lee, K. Najafi and C. Song, ‘A fabrication process for integrating polysilicon microstructures with post-processed CMOS circuitry’, J. Micromech. Microeng. Vol 10 (2000), pp. 380-386, describes Samsung's 18 mask (22 lithography steps) process using a machined 2 μm thick third polysilicon to protect a double polysilicon but not-yet-released MEMS accelerometer or gyroscope recessed in a 6 μm deep valley. Following standard LOCOS-based CMOS processing outside the location of this machined third polysilicon region protected by a 1.0 μm thick oxide and 0.12 μm thick LPCVD silicon nitride combination layers and involving a 16 hour duration p-well drive-in diffusion at 1200° C. in a nitrogen/oxygen ambient, the MEMS structure under the third polysilicon layer is released using a wet HF of buffered HF (BHF) etch penetrating the forming underlying cavity from the sides. Following this releasing step, photoresist is used to protect the CMOS circuitry including aluminum-based interconnects. No details are given about the packaging of the released structures.
An eleventh example of the importance of packaging is described in the paper by G.M. Rebeiz and J.B. Muldavin, ‘RF MEMS switches and switch circuits’, IEEE Microwave Magazine, December 2001, pp. 59-64. This paper indicates that MEMS based RF switches need to be packaged in inert atmospheres (nitrogen, argon, etc) and in very low humidity, resulting in hermetic or near-hermetic seals. It indicates that packaging costs are currently high and that the packaging technique itself may adversely affect the reliability of the MEMS switch. This paper reference indicates that since RF switches follow standard Newtonian's mechanics and, more specifically d'Alambert's equation of motion:mg″+bg′+k(go−g)=Fewhere m, and b are the mass and damping coefficient of the vibrating cantilever, shown in FIG. 4, g is the gap between the electrodes, k is the equivalent spring constant of the resonant frequency:{overscore (ω)}o=(k/m)1/2m is the mass of the oscillating part and Fe is the electrical force given by:2Fe=εAV2/(g+td/εr)2where ε is vacuum's permittivity constant, A is the area of the electrodes, V is the voltage divergence between the electrodes while td and εr are respectively the thickness and dielectric constant of the dielectric deposited over the fixed electrode. To the damping coefficient, b, of this motion equation is associated the very important quality, Q, factor:Q=k/{overscore (ω)}ob
This quality factor has to be as high as possible in order to allow high switching capability. Unfortunately, damping is limited by squeeze-film effect (removing the air underneath the cantilever) to about 0.2 to 5.0 for most designs at atmospheric pressure and can exceed 50-1000 when operated under vacuum.
U.S. Pat. No. 5,937,275 titled ‘Method of producing acceleration sensors’ (2.10.1. Robert Bosch GmbH), claims a method for producing sensors, especially acceleration sensors in which on a substrate (1) with a sacrificial layer (2), in an epitaxial application system, a silicon layer (4) is deposited that is deposited above the sacrificial layer (2) as a polysilicon layer (6), a first photoresist layer (7) being applied to the polysilicon layer (6) and being structured by optical methods as an etching mask, and structures (8) being introduced into the polysilicon layer (6) through the etching mask, which structures extend from the top side of the polysilicon layer (6) as far as the sacrificial layer (2), a sacrificial layer (2) being removed from beneath the structures (8), characterized in that the surface of the polysilicon layer (6) is post-machined in a smoothing process before the first photoresist layer (7) is applied. Amongst other things, additional claims cover the use of a photoresist plasma etch-back planarization process for the polysilicon layer, a chemical-mechanical polishing process of the polysilicon layer, a polysilicon starter layer under the polysilicon layer, a polysilicon layer over the sacrificial layer simultaneously to an epitaxial growth over the regions where no sacrificial layer is provided. This patent does not describe the protective cavity that Robert Bosch GmbH currently uses around the moving and/or particular component of its MEMS devices.
FIG. 5 shows an example of the surface micromachining performed at Robert Bosch GmbH, as reported on the Europractice web site: http://www.europractice. bosch.com/en/download/customer_support.pdf. In this technique a 380 μm thick cap wafer 11 and frit bonding 12 is used as to form a 75 μm high protective cavity over the 10.3 μm thick released polysilicon structures containing a gyroscope 10. Some details of this surface micromachining process are also available in the paper by M. Furtsch, M. Offenberg, H. Muenzel, J. R. Morante, ‘Comprehensive study of processing parameters influencing the stress and stress gradient of thick polysilicon layers’, SPIE Conference Proceedings ‘Micromachining and microfabrication process technology III, conference proceedings’, SPIE Vol. 3223, pp. 130-141, Austin Tex., Sep. 29-30, 1997.
In the process described in Furtsch's paper, the starting material is a 150mm (100) N-type 1-2 Ω.cm resistivity silicon wafer. The 2.5 μm thick Pad oxide is thermally grown on the substrate. The 0.45 μm thick Surface polysilicon layer is deposited using a standard 630° C. Low Pressure Chemical Vapor Deposition (LPCVD) process. The 0.45 μm thick Surface polysilicon layer is implanted with antimony and annealed at 1000° C. in an oxygen ambient to drive and activate the Sb dopant. There is no indication about the fabrication technique for the 1.6 μm thick sacrificial oxide. The 10.3 μm thick Structural ISDP (In-Situ Doped Polysilicon) layer is deposited as a 11.8 μm thick layer at a rate of 3.5 μm/minute and at a temperature of 1180° C. in a ASM Epsilon One Model-E2 single wafer epitaxy reactor using a standard trichlorosilane (SiHCl3), hydrogen (H2), and phosphine (PH3) process. The resulting 11.8 μm thick Structural ISDP layer has an average surface roughness (Ra) of 260 nm, which is unacceptable for further processing.
A chemical mechanical polishing (CMP) step is then used in the Furtsch process to reduce the thickness of the Structural ISDP to 10.3 μm and its surface roughness to about 5 nm. The silicon single crystals growing epitaxially over the silicon substrate regions opened through the 2.5 μm thick Pad oxide windows have a sheet resistance of 2 kΩ/sq. The as-grown polycrystalline structure being higher than 100 MΩ/sq., a 900° C. POCI3 doping is also performed, resulting in the growth of a 30 nm thick phosphorous glass (PSG) on top of the Structural ISDP. This thin grown PSG layer is removed using a standard HF etching solution. A protective oxide is grown at 900° C. to prevent the out-diffusion of phosphorus during the following 7 hours duration 1000° C. P-dopant drive-in in a nitrogen ambient. The protective oxide is then removed.
The Deep silicon etch patterns are generated using the technique described in the paper by M. Offenberg, F. Larmer, B, Elsner, H. Munzel and W. Riethmuller, ‘Novel process for a monolithic integrated accelerometer’, Digest of technical papers: Transducers '95—Eurosensors IX, Vol. 1, pp. 589-592, Stockholm, 1995.
The release of the Structural ISDP components is done using an HF vapor technique described in the paper by M. Offenberg, B, Elsner and F. Larmer, ‘HF vapor etching for sacrificial oxide removal in surface micromachining’, Extended Abstracts Electrochem. Soc. Fall Meeting, Vol. 94-2, pp. 1056-1057, Miami Beach, 1994.
No further details are given about the 1.3 μm thick metal layer, about the 380 μm thick Cap wafer or about the 75 μm Cavity. The resulting is a released MEMS device ready to be bonded to a protective Cap wafer, as shown in FIG. 6. Robert Bosch GmbH currently uses glass frit to bond this protective Cap wafer to the substrate as to provide an hermetic seal.
FIG. 7 summarizes the release of the Structural ISDP forming the moving components of the MEMS-based micro-sensors or micro-actuators as performed at Robert Bosch GmbH and as described in the above three references. The steps are as follows:                a. Selection of 150 mm (100) N-type 1-2 Ω.cm resistivity silicon wafer;        b. Thermal growth of 2.5 μm of Pad oxide, followed by patterning;        c. 630° C. LPCVD of 0.45 μm of Surface polysilicon, followed by an antimony implant, by a 1000° C. O2 anneal, and by patterning;        d. Deposition of 1.6 μm of Sacrificial oxide;        e. Deposition of 11.8 μm of Structural ISDP at a rate of 3.5 μm/minute and at a temperature of 1180° C. in a ASM Epsilon One Model-E2 using SiHCl3, H2 & PH3 gases, followed by a CMP of 1.5 μm to reduce the thickness of the Structural ISDP to 10.3 μm, followed by a 900° C. POCl3 doping, followed by the removal of the grown 30 nm thick PSG with HF solution, followed by the growth, at 900° C., of a protection oxide, followed by a 7 hours duration P-dopant drive-in in N2 at a temperature of 1000° C. and, finally, followed by the removal of the protection oxide;        f. Deposition and patterning of a 1.3 μm metal layer;        g. Deep silicon etch of the Structural ISDP using the technique described in the following reference M. Offenberg, F. Larmer, B, Elsner, H. Munzel and W. Riethmuller, ‘Novel process for a monolithic integrated accelerometer’, Digest of technical papers: Transducers '95—Eurosensors IX, Vol. 1, pp. 589-592, Stockholm, 1995; and        h. Release of Structural ISDP components with HF vapor using the technique described in the paper by M. Offenberg, B, Elsner and F. Larmer, ‘HF vapor etching for sacrificial oxide removal in surface micromachining’, Extended Abstracts Electrochem. Soc. Fall Meeting, Vol. 94-2, pp. 1056-1057, Miami Beach, 1994.        
Additional details of this surface micromachining process are also available in the reference http://www.imec.be/SUMICAP/Welcome.html#who.
The SUMICAP (SUrface Micromachined enCAPsulation on wafer-level) project carried out by IMEC, Bosch and STS within the framework of the Information Societies Technology (IST) program of the European Commission (contract number IST-1999-10620) between January 2000 and December 2002 is intended to develop a wafer-level encapsulation technique for MEMS using surface micromachined membranes over a device that needs to be encapsulated in a vacuum (below 100 Pa) or controlled atmosphere. This monolithic wafer-level packaging technique should be capable of covering 1 mm by 1 mm MEMS devices having high aspect ratio trenches (1:5); survive standard plastic molding; use less chip area and material than the current capping process; provide a 50% reduction of the total chip cost; and a vacuum in the cavity below 100 Pa.
The project managed by IMEC uses the following steps: sacrificial oxide layer deposition, membrane layer deposition, sacrificial oxide etching using the standard STS equipment, sealing layer deposition and Interconnections. The expected result is a wafer-level surface micromachined encapsulation in a plastic molding of an accelerometer demonstrator optimized using Bosch's extensive simulations to determine the required thickness and stress of the membrane and sealing layer, the number of supports and the optimal sensor design.
A review of prior art indicates that there is a need to improve the packaging techniques of MEMS devices to ensure higher yields, higher performance and improved reliability. Most of the cited prior art describes the need for bonding multiple substrates to get the required protective cavity around the moving and/or particular component of the MEMS device, in particular U.S. Pat. No. 5,668,033; U.S. Pat. No. 5,783,749; U.S. Pat. No. 5,952,572; U.S. Pat. No. 6,140,144; U.S. Pat. No. 6,232,150; U.S. Pat. No. 6,265,246; U.S. Pat. No. 6,297,072; U.S. Pat No. 6,335,224; the paper by B. Lee, S. Seok, J. Kim, and K. Chun, ‘A mixed micromachined differential resonant accelerometer’, Work supported by ADD (Agency for Defense Development) through ACRC (Automatic Control Research Center) under Grant AC-041 and by the Brain Korea21 Project; the paper by B. Lee, C. Oh, S. Lee, Y. Oh and K. Chun, ‘A vacuum packaged differential resonant accelerometer using gap sensitive electrostatic stiffness change effect’, Work supported by ADD (Agency for Defense Development) through ACRC (Automatic Control Research Center) under Grant AC-041; and the paper by Gianchandani, H. Kim, M. Chinn, B. Ha, B. Lee, K. Najafi and C. Song, ‘A fabrication process for integrating polysilicon microstructures with post-processed CMOS circuitry’, J. Micromech. Microeng. Vol 10 (2000), pp. 380-386.;
One of the cited references reviews the effect of the residual vacuum on the undesirable reduction of the Q factor of RF switches operating at very high frequencies as described in G.M. Rebeiz and J.B. Muldavin, ‘RF MEMS switches and switch circuits’, IEEE Microwave Magazine, December 2001, pp. 59-64; U.S. Pat. No. 5,937,275; the reference at http://www.europractice.bosch.com/en/download/customer support.pdf as shown in FIGS. 5, 6 and 7, and the paper by M. Furtsch, M. Offenberg, H. Muenzel, J. R. Morante, ‘Comprehensive study of processing parameters influencing the stress and stress gradient of thick polysilicon layers’, SPIE Conference Proceedings ‘Micromachining and microfabrication process technology III, conference proceedings’, SPIE Vol. 3223, pp. 130-141, Austin Tex., Sep. 29-30, 1997 (FIG. 5). In FIG. 5, S1 represents the wafer thickness of 675±15 μm; S2 represents the pad oxide layer thickness of 2.5±0.15 μm; S3 the represents the surface polysilicon layer thickness of 0.45±0.05 μm; S4 represents the sacrificial oxide layer thickness of 1.6±0.2 μm, S5 represents the structural ISDP layer thickness of 10.3±1.0 μm; S6 represents the metal layer thickness of 1.3±0.2 μm; S7 represents the cap wafer thickness of 380±15 μm; and S8 represents the cavity height of 75±25 μm.
It is known that Direct Wafer Bonding (DWB) of two substrates is not a suitable technique for vacuum packaged MEMS because of its required very high 1000° C. bonding temperature. The Glass Frit Bonding technique discussed in some of the afore-mentioned Bosch Prior Art references is also unsatisfactory because its associated poor vacuum level degrades the Q-factor of most gyroscopes, accelerometers, RF switches and many other MEMS-based devices requiring packaging under a vacuum typically better than 1 Pa. This explains Samsung's upper discussed Anodic Bonding. This technique still requires bonding of multiple substrates at temperatures of about 500° C. at which the mobility of the positive ions (typically Na+) and the reactivity of the glass-silicon interface cause oxygen from the glass to be transported under the existing electric field and cause its combination with the interfacial silicon as to form a permanent SiO2 bond.
Unfortunately, the increased demand for higher yield and lower cost processes for the production of CMOS integrated MEMS devices in cost-sensitive markets, such as automotive and consumer electronics, requires the replacement of anodic bonding or other multiple substrates bonding techniques by a lower cost, single substrate, CMOS compatible wafer-level encapsulation technique. The above-described IMEC-Bosch-STS SUMICAP project on-going within the IST program of the European Commission (http://www.imec.be/SUMICAP/Welcome.html#who) is intended to develop such a wafer-level encapsulation technique for MEMS in standard plastic moldings using surface micromachined membranes with a 100 goal which is will still very restrictive for the high performance (high Q-factor) micro-gyros, micro-accelerometers, differential resonant accelerometers and other MEMS-based devices requiring a residual vacuum level better than 1 Pa. Unfortunately, little is really known about this program.